The present invention relates to a semiconductor memory and more particularly to a semiconductor memory having error correcting means using an error correcting code.
As a measure to cope with errors, there is known a method in which a redundant bit (check bit) for an error correcting code (hereinafter abbreviated as ECC) is added and encoding and decoding circuits are provided on the chip of a semiconductor memory to correct data, as disclosed in Yamada, J., et al. "A submicron VLSI Memory with a 4b-at-a-Time Built in ECC Circuit" ISSCC digest of Technical Papers, pp. 104-105. Feb. 1984.
With respect to this method, a question arises as to the scale of the encoding and decoding circuits. However, if a cyclic code is used as an ECC and serial encoding and decoding are conducted by positively using the nature of the cyclic code, a small circuit may be used. This is particularly effective for a memory which serially reads and writes data. This method, however, has the following problem. Although n cycle operations of the encoding circuit are required for writing data, 2n cycle operations of the decoding circuit (n cycles for syndrome generation and n cycles for error correcting) are required for reading data. The access times are different respectively for reading and writing, so that the user finds difficulty in making use of the memory.